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10/25/2014 Cadence releases IP for 3D memory

Cadence Design Systems is offering verification IP (VIP) supporting the design of 3D memory interfaces on standards including Wide I/O 2, Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM) and DDR4 3D Stacking (DDR4-3DS). The VIP models include direct memory access for read, write, save, pre-load and comparison of memory contents, robust assertions, error configurability,...

richard wilson

10/24/2014 Microchip aims parallel flash at consumer gear

Microchip has introduced a general-purpose fast parallel flash memory chip. SST38VF6401B is a 4M x16 CMOS with a split-gate cell design and thick-oxide tunneling injector for better reliability and manufacturability. Operating is from 2.7 to 3.6V and the memory is partitioned into uniform 32kword and non-uniform 8kword blocks. Various levels of protection are provided, including...

steve bush

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